The present invention relates to modulation techniques, and more particularly to phase error detection and correction of phase error between differential signals, such as in-phase and quadrature phase carrier signals of a quadrature oscillator.
Many small networks are commonly connected through a set of wires. Wired networks provide a certain level of convenience but have many limitations such as various cable management and convenience issues. For various reasons, wireless LAN (WLAN) technology is becoming more popular. Radio frequency (RF) appears to be the technology of choice for establishing a viable WLAN. The typical environment for wireless communications, however, is very noisy and not optimal for communications. For example, most homes and workplaces include many electronic devices resulting in an electronically noisy environment that may interfere with WLAN communications, such as microwave ovens, garage door openers, radios, television sets, computer systems, etc. Further, the communication medium between wireless devices is dynamic and constantly changes. For example, most environments or rooms include multiple reflective services, creating multipath noise. Movement of items or devices or the like such as hands, bodies, jewelry, mouse pointers, etc., or activation of electronic devices, such as cooling fans or the like, affects the overall wireless communication path and potentially degrades wireless communication performance. In summary, wireless communications must be made through a dynamic and unpredictable medium.
In spite of the limitations of the wireless medium, consumers are demanding high-speed wireless applications and relatively high quality of service (QOS) applications. Such applications include media streams, which further include any combination of video and audio information and other data. Because of the dynamic and unpredictable environment through which wireless communications must be made, wireless communications are generally less robust and less reliable than corresponding wired communications. Also, A significant amount of overhead is required for successful wireless communications. For example, frames or packets of information submitted through the wireless media typically include a known preamble to enable the receiving device to measure the noise and distortion effects of the wireless medium. Collision detection techniques, such as commonly used in Ethernet wired environments, are not particularly useful in wireless communications since a transceiver is unable to receive a signal while transmitting. Therefore, many rules and timing constraints must be followed for wireless devices to communicate with each other in half duplex mode.
It is imperative that wireless transceivers utilize the wireless medium in the most efficient manner possible to maximize data throughput and to meet bandwidth requirements. In one technique, information is encoded onto an RF carrier by modulating the amplitude and phase angle. The phase modulation/demodulation is achieved by using pairs of mixers driven by quadrature local oscillator (LO) signals. The two phases of the local oscillator, designated I (in-phase) and Q (quadrature phase), are at the same frequency, but the Q phase is delayed one quarter cycle or period (90 degrees) with respect to the I phase carrier signal. The amount of data that can be transmitted at a given carrier frequency is proportional to the accuracy of the I/Q phase relationship.
In an exemplary embodiment, the two local oscillator phases are derived from a single voltage controlled oscillator (VCO) to obtain coherency. However, imperfections in the quadrature generation and/or distribution circuits typically cause quadrature phase errors. In order to obtain high data transmission rates, the I/Q phase relationship must not deviate from 90 degrees by more than few degrees. This has proven difficult to achieve in typical wireless transceiver configurations. For example, with a local oscillator frequency of 2.5 gigahertz (GHz), a timing error of 1.1 picoseconds (ps) is equivalent to one degree of phase error. Within the transceiver circuitry, a mismatch in parasitic capacitance of 11 fempto Farads (fF) across a 100-ohm resister can generate a one-degree phase error. An ft mismatch (where xe2x80x9ctxe2x80x9d is shown as Greek tau symbol or xe2x80x9cxcfx84xe2x80x9d in the Figures) of a bipolar junction transistor (BJT) of ten percent may also generate about one degree phase error at RF. A local oscillator chain of one or more buffer stages may cause accumulated timing errors between I and Q that may exceed several degrees.
It is desired to detect and reduce or otherwise eliminate phase errors between differential signals, such as the I/Q carrier signals of a quadrature oscillator. The reduction in phase error increases the amount of data that can be transmitted in accordance with the RF quadrature modulating technique.
A phase error detector according to an embodiment of the present invention may be used to detect and correct any phase error between positive and negative polarities of first and second differential signals. The first and second differential signals may be, for example, the carrier signals of a quadrature generator. The quadrature generator provides positive and negative in-phase (I) carrier signals and positive and negative quadrature phase (Q) carrier signals and receives a phase error signal. The quadrature oscillator attempts to maintain the I and Q carrier signals at a one-quarter period phase differential with respect to each other based on the phase error signal. It is appreciated, however, that phase error detectors according to embodiments of the present invention may be employed for other types of circuits and applications, such as phase-locked loop (PLLs), voltage controlled oscillators (VCOs), etc.
The phase error detector includes a summing network and first and second mixer circuits. The summing network develops four sum signals by summing the positive polarity signal of the first differential signal with the positive polarity signal of the second differential signal, the negative polarity signal of the first differential signal with the negative polarity signal of the second differential signal, the positive polarity signal of the first differential signal with the negative polarity signal of the second differential signal, and the negative polarity signal of the first differential signal with the positive polarity signal of the second differential signal. The first mixer circuit develops a first polarity signal of the phase error signal based on the first and second sum signals, and the second mixer circuit develops a second polarity signal of the phase error signal based on the third and fourth sum signals. The resulting phase error signal is the differential of the first and second polarity signals.
In one embodiment, the summing network removes DC from the first, second, third and fourth sum signals. The first mixer circuit is responsive to the positive portion of the first and third sum signals and develops the first polarity signal of the phase error signal as a combined signal. Likewise, the second mixer circuit is responsive to the positive portion of the second and fourth sum signals and develops the second polarity signal of the phase error signal as a combined signal. In a particular embodiment, for example, the sum signals are pulsed voltage signals that activate transistor switches. The transistors draw averaged and combined current signals through a bias resistor to develop a phase error polarity signal.
In another embodiment, the summing network comprises an impedance bridge network. In a more specific embodiment, the impedance bridge network is a capacitive bridge network that includes first, second, third and fourth capacitive legs coupled together at first, second, third and fourth primary junctions. The positive polarity signal of the first differential signal is received at the first primary junction coupling the first and fourth capacitive legs. The negative polarity signal of the first differential signal is received at the third primary junction coupling the second and third capacitive legs. The positive polarity signal of the second differential signal is received at the second primary junction coupling the first and second capacitive legs. The negative polarity signal of the second differential signal is received at the fourth primary junction coupling the third and fourth capacitive legs. Each capacitive leg includes two capacitors coupled together at an intermediate junction to provide a corresponding sum signal. In particular, the first capacitive leg provides the first sum signal, the second capacitive leg provides the fourth sum signal, the third capacitive leg provides the third sum signal, and the fourth capacitive leg provides the second sum signal at respective intermediate junctions. The two capacitors of each capacitive leg of the capacitive network may be matched with each other, which is particularly useful when the input impedance of the mixers is primarily capacitive. Also, all the capacitors of the capacitive bridge network may be matched.
Each of the mixer circuits may include a matched pair of bipolar transistors with common-coupled collectors. The base of each transistor receives a corresponding one of the four sum signals. In particular, the first and third sum signals are provided to one matched pair of transistors to develop the first polarity signal and the second and fourth sum signals are provided to the other matched pair of transistors to develop the second polarity signal of the phase error signal. A bias circuit is provided to bias the transistors of the mixers. In one embodiment, a pair of bias resistors are each coupled between a power supply signal and a respective one of the common-coupled collectors of the first and second matched pairs of bipolar transistors. The bias resistors may be matched with each other for symmetry. The bias resistors may alternatively be inductors or the like or may be collectively replaced by a current mirror.
A bias circuit may be provided and coupled to the mixers. In one embodiment, four bias devices are coupled between a bias signal and a respective one of the intermediate junctions of the capacitive legs of the capacitive bridge network. The bias devices may be resistors, but may alternatively be current sources or inductors or the like. For the bipolar transistor-based configuration of the mixers, the bias devices are each coupled to a bias signal and to a respective base of the four transistors of the mixer circuits. Two filters may be provided, each coupled between the collectors and emitters of a respective one of the first and second matched pairs of bipolar transistors. The filters divert AC current to ground so that only DC current flows through the bias resistors. The filters may be capacitors or other more sophisticated types of filters.
A quadrature generator system with phase error detection feedback in accordance with embodiments of the present invention includes a quadrature generator and a phase error detector. The quadrature generator develops positive and negative square-wave I carrier signals and positive and negative square-wave Q carrier signals and receives a differential phase error signal for correcting phase error between the I and Q carrier signals. The phase error detector is similar to that described above and includes first and second mixer circuits and a summing circuit for providing four sum signals. The first mixer circuit combines first and second sum signals and develops a first polarity signal of a differential phase error signal. The second mixer circuit combines third and fourth sum signals and develops a second polarity signal of the differential phase error signal.
It is appreciated that a radio transceiver may be implemented with a phase error detector in accordance with the present invention. The receiver includes I and Q radio frequency (RF) mixers that receive the I and Q carrier signals, respectively, to separate the carrier signals from the I and Q portions of the received signal. The transmitter includes similar I and Q RF mixers that mix the I and Q carrier signals, respectively, with I and Q transmit signals, respectively, to develop a combined signal for transmission. The radio transceiver includes a quadrature oscillator with phase error detection feedback in accordance with embodiments of the present invention that enables accurate I and Q carrier signals. It is noted that a single phase error detector may be employed for both transmit and receive circuits. A switched phase error detector is contemplated for half-duplex operation in which only one of the transmit and receive circuits is operational at any given time. Alternatively, separate transmit and receive phase error detectors may be provided adjacent corresponding transmit and receive mixers for improved accuracy.
The present disclosure also describes a method of providing a phase error signal indicative of any phase error phase error between positive and negative polarities of a first and second differential signals. The first and second differential signals each include positive and negative polarity signals. The method includes combining the positive polarity signals of the first and second differential signals and providing a first sum, combining the negative polarity signals of the first and second differential signals and providing a second sum, combining a first positive polarity signal and a first negative polarity signal of the first and second differential signals and providing a third sum, and combining a second positive polarity signal and a second negative polarity signal of the first and second differential signals and providing a fourth sum. The method further includes mixing the first and third sums to generate a first polarity phase error signal, mixing the second and fourth sums to generate a second polarity phase error signal, and providing the phase error signal as the difference between the first and second polarity phase error signals.
The combining of the respective I and Q signals may include summing the respective signals together. The method may also include removing DC from the first, second, third and fourth sums prior to mixing. The method may further include generating a first signal responsive to a positive portion of the first sum, generating a second signal responsive to a positive portion of the third sum, and combining the first and second signals to achieve the first polarity phase error signal. Also, the method may include generating a third signal responsive to a positive portion of the second sum, generating a fourth signal responsive to a positive portion of the fourth sum, and combining the third and fourth signals to achieve the second polarity phase error signal.